a) Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device with MOS transistors (insulated gate type field effect transistors), and more particularly to techniques capable of easily lowering a variation in threshold voltages of MOS transistors by forming a wiring layer on an interlayer insulating film including a hydrogen containing film, forming a silicon nitride film as a surface protection film (passivation film) on the wiring layer, and thereafter performing heat treatment to lower interface state density.
b) Description of the Related Art
In a semiconductor device having a surface protection film, for example, as shown in FIG. 6, on the surface of an interlayer insulating film 1, wiring layers 2A and 2B near to each other are formed, and a silicon nitride film 3 as the surface protection film is formed on the interlayer insulating film 1, covering the wiring layers 2A and 2B (e.g., refer to JP-A-63-244628).
A channel region of a MOS transistor may have process damages during manufacture. As a method of lowering a variation in threshold voltages of MOS transistors by lowering interfacial energy levels generated by process damages, a hydrogen annealing process is known which performs heat treatment of a wafer in a nitrogen gas atmosphere which contains hydrogen after wiring layers and the like are formed (e.g., refer to Technical Report of the Institute of Electronics, Information and Communication Engineers, Vol. 97, No. 508, SDM97-181 (Jan. 23, 1998), pp. 25-32).
As a similar nitrogen annealing process, a method of performing heat treatment in a nitrogen gas atmosphere for a semiconductor device shown in FIG. 7 is known (e.g., refer to JP-A-HEI 8-45926). FIG. 7 shows a transistor in a MOS type IC. As shown, on the surface of a semiconductor substrate 5 made of silicon or the like, a field insulating film 6 is formed through local oxidation of silicon (LOCOS). On the silicon substrate surface in an active area where the field insulating film 6 is not formed, a MOS transistor Tr is formed.
The transistor Tr is formed by the following processes. The silicon substrate surface is oxidized through thermal oxidation or the like to form a gate insulating film A. On this gate insulating film A, a polysilicon layer, a silicide layer and a hydrogen containing SixNy (or SixOyNz) film are sequentially formed. This stacked-layer structure is patterned by well-known photolithography techniques and anisotropic dry etching to form a gate electrode layer B. The SixNy (or SixOyNz) film functions as an antireflection film for mitigating the influence of reflection light from the silicide layer during the exposure of the photolithography process. After the etching process, the SixNy (or SixOyNz) film is left as a layer C on the gate electrode layer B, having the same pattern as the gate electrode layer B. By using as a mask the lamination of the gate insulating film A, gate electrode layer B, and SixNy (or SixOyNz) film C and field insulating film 6, impurities are selectively introduced to form a source region P1 and a drain region P2 having a relatively low impurity concentration. Side spacers E1 and E2 of silicon oxide or the like are formed on side walls of the lamination of the gate insulating film A, gate electrode layer B and SixNy (or SixOyNz) film C. Then, a source region Q1 and a drain region Q2 having a relatively high impurity concentration are formed by a selective impurity doping process by using as a mask the lamination of the gate insulating film A, gate electrode layer B and SixNy (or SixOyNz) film C, the side spacers E1 and E2 and field insulating film 6. A lightly doped drain (LDD) structure can therefore be formed.
A barrier film 7 of silicon nitride is formed over the substrate, covering the transistor Tr and field insulating film 6. On this barrier film 7, an interlayer insulating film 8 made of, for example, borophospho silicate glass (BPSG), is formed. Contact holes 8s and 8d are formed through the stacked-layer structure of the barrier layer 7 and interlayer insulating film 8, reaching the surfaces of the source region Q1 and drain region Q2. In this state, heat treatment is performed in a hydrogen containing nitrogen gas atmosphere. Hydrogen in the SixNy (or SixOyNz) film C and hydrogen in the heat treatment atmosphere are supplied to the channel region of the transistor Tr. Interfacial energy levels of the channel region therefore lower. The barrier film 7 suppresses the diffusion of hydrogen in the SixNy (or SixOyNz) film C into the interlayer insulating film 8.
In the surface protection structure shown in FIG. 6, the dielectric constant of the silicon nitride film 3 is as high as about 7. Therefore, the electrostatic capacitance between the wiring layers 2A and 2B becomes large, which hinders a high speed operation and a large operation margin.
In order to reduce the wiring capacitance, it can be thought of that the silicon nitride film 3 is formed as thin as indicated by a broken line 3a in FIG. 6 and as can form a groove GV between the wiring layers 2A and 2B. Since air having the dielectric constant of 1 is filled in the groove GV, the wiring capacitance can be reduced.
However, if the silicon nitride film 3 is made thin, the hydrogen annealing process for lowering interfacial energy levels is associated with the following problems. If the hydrogen annealing process is performed before the silicon nitride film 3 is formed, hillocks (lateral hillocks) are formed laterally from the wiring layers 2A and 2B made of Al or Al alloy, which may cause a short circuit between the wiring layers 2A and 2B. On the other hand, if the hydrogen annealing process is performed after the silicon nitride film 3 is formed, interface state density cannot be lowered because hydrogen is hard to transmit through the silicon nitride film 3.
If the silicon nitride film 3 is to be formed by plasma chemical vapor deposition (CVD), silane, ammonium or the like is used as source gas. The silicon film 3 formed by using such gas has not the composition of perfect Si3N4, but contains unreacted hydrogen (such as N—H and Si—H). Although this unreacted hydrogen released by the hydrogen annealing process contributes to lowering the interfacial energy levels, the contribution degree is insufficient. The interfacial energy level lowering effect is insufficient particularly when the silicon nitride film 3 is made thin as described above. It can be also through of that a Ti layer as a barrier metal layer is formed as the lowermost layer of the wiring layers 2A and 2B to prevent the formation of hillocks. However, the Ti layer absorbs hydrogen and the interfacial energy level lowering effect is further lowered (refer to the previously-cited “Technical Report”).
In the case of the hydrogen annealing process applied to the transistor Tr shown in FIG. 7, hydrogen in the SixNy (or SixOyNz) film C is supplied to the channel region of the transistor Tr and hydrogen in the heat treatment atmosphere is also supplied via the contact holes 8s and 8d to the channel region. It is necessary to provide two hydrogen supply sources and the process control becomes complicated.
If a silicide layer is to be formed on the source region Q1, gate electrode layer B and drain region Q2 by a so-called salicide process, it is necessary to remove the SixNy (or SixOyNz) film C before the hydrogen annealing process. Therefore, this film cannot be utilized as the hydrogen supply source during the hydrogen annealing process. In other words, the salicide process cannot be adopted if the film C is used as the hydrogen supply source.